Hongkong

Chengdu

Shenzhen

Job Responsibilities:

1. Responsible for the digital logic design of chip sub-module, write design documents and complete code development according to design requirements;

2. Responsible for module unit verification, according to design specifications, complete unit verification environment construction, use case design and code debugging, participate in chip integration verification and system verification;

3. Participate in FPGA verification work, complete verification scheme and system joint debugging.

Job requirements:

1. Master degree or above (or excellent bachelor), major in microelectronics and communication electronics;

2. More than two years of digital IC design experience;

3. Proficient in Verilog language, familiar with the basic process of ASIC design and various EDA tools;

4. Experience in SOC and digital-analog hybrid chip design is preferred;

5. Experience in comprehensive, STA and FPGA design is preferred;

6. Good health, strong learning ability, communication skills and teamwork spirit.

Hongkong

Chengdu

Shenzhen

Job Responsibilities:

1. According to the needs, formulate the verification plan and write the verification plan;

2. Be able to use VCS to build a verification platform, build test cases, and conduct simulation and debugging;

3. Proficient in using SV to write reference models, assertions, and functional coverage codes.

Job requirements:

1. Bachelor's or master's degree in electronic engineering, communication, microelectronics or related disciplines;

2. Bachelor degree with 3 years or more working experience, master's degree or above with 1 year or more experience;

3. Proficient in using VCS, Verdi and other related EDA tools;

4. Familiar with C/systemC, perl/shell, Makefile;

5. CET4 or above in English;

6. Integrity and integrity, good communication skills and teamwork skills, relevant experience is preferred.

Hongkong

Chengdu

Shenzhen

Job Responsibilities:

1. According to the requirements, formulate an end-to-end verification strategy, formulate a verification plan, and write a verification plan;

2. Be able to use VCS to build a verification platform, build test cases, and conduct simulation and debugging;

3. Proficient in using SV to write reference models, assertions, and functional coverage codes.

Job requirements:

1. Bachelor's or master's degree in electronic engineering, communication, microelectronics or related disciplines;

2. Bachelor degree with 8 years or above work experience, master's degree or above with 5 years or more experience;

3. Proficient in using VCS, Verdi and other related EDA tools;

4. Familiar with C/systemC, perl/shell, Makefile;

5. Be able to guide the work of junior verification engineers;

6. CET4 or above in English;

7. Integrity and integrity, good communication skills and teamwork skills, relevant experience is preferred.

Hongkong

Chengdu

Shenzhen

Shanghai

Job Description:

Complete the whole process netlist delivery for the backend, including clock scheme design, floorplan design, netlist synthesis, Formality verification, STA timing analysis.

Job requirements:

1. Have RTL to netlist delivery related skills, including netlist synthesis, MBIST/DFT insertion, static timing analysis, netlist form verification, etc., familiar with synopsys synthesis, primetime, formality and other EDA tools;

2. Familiar with RTL design, able to fully communicate with front-end engineers, support RTL design optimization, clock reset scheme design design and low power consumption design experience is preferred;

3. Familiar with the process and requirements of back-end PR, can support back-end completion of netlist signoff, familiar with standard process libraries, and have experience in supporting back-end completion of FloorPlan, clock synthesis, and power consumption analysis is better.

Hongkong

Chengdu

Shenzhen

Job Responsibilities:

That is, product QA, participate in the establishment and improvement of chip development quality management system, responsible for the quality control of project life cycle development process and results.

1. Responsible for formulating the project quality assurance plan and implementing it according to the plan; Identify the quality risks of project development, regularly report the quality status of the project, and promote quality problem solving and risk prevention;

2. Responsible for providing process training, consultation and guidance to the project team, and supervising the implementation of project development in accordance with the defined process;

3. Responsible for quality management in the process of product development, excavating links that need to be improved, good practices, checklists, etc., and establishing or optimizing the process specifications of each link of the project;

4. Responsible for product development quality review and closed-loop to the design source, analyze data related to the chip development process, organize the analysis and improvement of major quality problems, and promote the improvement of delivery quality and efficiency;

5. Responsible for the management and maintenance of the configuration library, and implement the configuration management of the project according to the process requirements.

Qualifications:

1. Full-time bachelor degree or above in communication, electronics, computer or related majors;

2. More than five years of QA experience in electronic product related R&D enterprises, chip design industry related experience is preferred;

3. Familiar with electronic product development process and product knowledge, with strong business understanding;

4. Master the theoretical knowledge of quality; Familiar with quality retrospection and statistical engineering methods; Proficient in the use of the five tools and seven techniques of quality;

5. Meticulous and rigorous work, with strong systematic thinking ability and planning ability, coordination and communication ability and execution ability;

6. Experience in end-to-end quality management based on IPD product development is preferred.